The introduction of silicon germanium (SiGe) epitaxial technology has allowed GaAs high-frequency (microwave) transistors to be replaced with silicon transistors in numerous applications. For example, while standard silicon bipolar transistors could not operate reliably above 1 GHz, SiGe Heterostructure Bipolar Transistors (HBT) are now beginning to appear in circuits designed to operate above 10 GHz.
However, SiGe devices fabricated on Silicon (Si) substrates are subject to a number of inherent restrictions. Due to the large lattice mismatch between silicon and germanium (Ge), an alloy SiGe layer grown on top of a silicon substrate or single-crystal surface must remain below a certain critical thickness in order to prevent relaxation through the formation of threading dislocations. Such defects can propagate through the Si and SiGe layers and cause the devices fabricated using these layers to experience high percentages of failure. Consequently, the overall yield of such a fabrication process will be far lower than would generally be acceptable in comparison to rival fabrication technologies.
Thus, control of strain in Si and SiGe layers deposited on various semiconductor surfaces is a challenging area of development and important to the fabrication of devices and circuits. Specifically, the strain in the epitaxial layer (i.e. the layer grown/deposited on the substrate) alters the electrical characteristics of the composite semiconductor material. That is, various parameters such as electron and hole mobility, energy bandgap, etc. are known to change as a result of a change in the ‘built-in’ strain associated with matching the atomic lattice structure of the epitaxial layer with that of the layer (e.g. the substrate or another between layer) onto which the epitaxial layer is grown.
The lattice strain within the deposited or grown layers may alter the susceptibility of the layers to various etching or dissolving solvents. In the construction of micro-mechanical devices (MEMS) strain in the deposited or grown layers and the morphology of such layers are important variables in the device commercial fabrication and yield at which devices can be successfully reproduced.
The availability of high-quality SiGe substrates would permit the development of new devices with thicker, lattice-matched SiGe, tensile-strained Si or SiGe layers, or strain-compensated Si/SiGe structures. However, a SiGe substrate would typically have an atomic spacing (lattice constant) different from the epitaxial layer grown on top of it; and, therefore growing a Si or SiGe epitaxial layer—with a different percentage of Ge—would induce different strain conditions.
Moreover, until recently, the only available SiGe substrates were virtual SiGe substrates; these are actually Si substrates with a thick, relaxed SiGe buffer. However, the defect density of virtual SiGe substrates is around 104 cm−2 which compared to single crystal silicon wafers is quite poor and, in the context of Silicon VLSI manufacturing, intolerable. In spite of this, good SiGe n-type (p-type) field-effect transistors with relatively high electron (hole) mobility have been realized on these types of substrates.
The recent commercial introduction of single-crystal SiGe substrates manufactured using the Czochralski technique, like their single crystal silicon wafer counterparts, promises to further improve device characteristics, percentage yield and to potentially allow for large-scale manufacturing of Si/SiGe FETs and HEMTs. These devices could be constructed on the aforementioned high-quality SiGe substrates having a percentage yield acceptable to the general practices and cost structures of the Si VLSI industry. This would make possible, for example, CMOS VLSI circuits, like those used in computer microprocessors and memory chips, with increased speed of operation or lower power consumption than those without SiGe. Other potential applications include novel optoelectronic devices and Ge-based thermoelectric generators.
The pitfall, thus far, has been that the epitaxial deposition of SiGe directly on SiGe substrates results in an interface between the two layers that suffers from unacceptable strain conditions and poor morphology which in turn causes lattice defects within each of the two layers; thereby significantly reducing the smoothness of the interface. Consequently, the epitaxial layer is of poor quality and uniformity, leading to a very rough surface morphology which in turn negatively impacts subsequent processing steps. It is now well established that the quality and performance of electronic devices is directly related to the smoothness of interfaces between the substrate and the epitaxial layer and between layers; the smoother the interfaces, the better the devices fabricated.
The problem of non-uniform growth or poor surface morphology (i.e. smoothness) may be compounded when growth of a SiGe epitaxial layer is to take place on a mixed-topology or patterned surface. For example, a surface with regions of oxide (silicon dioxide) and SiGe single crystal surfaces will induce different growth rates for the SiGe epitaxial layer on the different surfaces which will in turn cause the grown (or deposited) epitaxial layer to have a poor surface morphology.
Thus, there is a desire to provide a method of depositing high-quality Si or SiGe epitaxial layers on SiGe substrates in which the surfaces of the deposited layers are substantially free of lattice defects and are thus substantially uniform. Moreover, it would be desirable for the interfaces between the substrate and the deposited layers and between layers to be smooth and substantially free of lattice defects.